Gate driver circuits, including high-side and low-side drivers, are used to drive power MOSFET or IGBT output transistors which are used in high voltage applications, such as motors. In some applications, the high-side driver is used to drive an N-channel power MOSFET in the high-side configuration which operates up to 600V. Conventional high voltage gate driver circuits integrate both the high-side gate driver and the low-side gate driver onto the same integrated circuit. FIG. 1 is a schematic diagram of a conventional high voltage gate driver circuit. In the example configuration shown in FIG. 1, a high voltage gate driver circuit 10 includes a gate driver integrated circuit 11 (indicated by the dotted line) housing the high-side gate driver circuit and the low-side gate driver circuit. The high voltage gate driver circuit 10 is disposed to drive a pair of power switches connected in series between a high input supply voltage VIN (node 40) and the ground potential (node 42). In the present illustration, the power switches are N-channel power MOSFETs M1 and M2. Also, in the present illustration, the high input supply voltage VIN is 600V or above. The N-channel MOSFET M1 thus has to operate up to 600V. The pair of N-channel power MOSFETs M1 and M2, under the control of the high-side drive signal HO (node 25) and the low-side drive signal LO (node 32), are alternately turned on and off to generate an output voltage signal Vs (node LX) to drive a load. The power MOSFETs M1 and M2 can be integrated onto the gate driver integrated circuit 11. More often, the power MOSFETs M1 and M2 are discrete devices and in some cases, the discrete devices are co-packaged with the gate driver integrated circuit 11 (indicated by the dot-dash line).
High voltage gate driver circuit 10 receives a high-side input signal HIN (node 14) and a low-side input signal LIN (node 16). The low-side input signal LIN is coupled to a low-side driver circuit 26 which drives a gate driver 30 to generate the low-side drive signal LO to drive power switch M2. Meanwhile, the high-side input signal HIN is coupled to high-side control circuitry, including a pulse generator 18, a level shift and high-side driver circuit 20, a pre-driver 22 and a gate driver 24. The gate driver 24 generates the high-side drive signal HO to drive power switch M1.
The high voltage gate driver circuit 10 receives a logic supply voltage Vdd (node 12). The logic supply voltage Vdd supplies the low-side control circuitry, such as the low-side driver circuit 26 and the gate driver 30. Because the high-side control circuitry is coupled to drive the high-side power switch M1 operating at a high input supply voltage VIN, some of the high-side control circuitry are formed in a high voltage floating tub and are supplied by a boost supply voltage VB on a boost node BST. The floating tub is biased to the output voltage Vs (node LX) which is referred to as a floating supply voltage. More specifically, the pulse generator 18 is operated on the logic supply voltage Vdd and then the signals are level-shifted up so that the level shifter and high-side driver circuit 20, the pre-driver 22, and the gate driver 24 are formed in the high-voltage floating tub and are supplied by the boost supply voltage VB.
The boost supply voltage VB is generated from the logic supply voltage Vdd and a boost capacitor CB. More specifically, the capacitor CB is connected between the boost node BST and the output voltage Vs (node LX). A diode D1 is interposed between the logic supply voltage Vdd (node 12) and the top plate of the capacitor CB (node BST). More specifically, the anode of diode D1 is connected to the logic supply voltage (node 12) and the cathode of diode D1 is connected to the top plate (node BST) of the capacitor CB. Diode D1 functions to charge the boost capacitor CB when MOSFET M2 is turned on and to provide reverse blocking when MOSFET M1 is turned on. That is, diode D1 allows current to flow from the logic supply voltage Vdd to charge up capacitor CB in a forward bias direction when MOSFET M2 is turned on. However, diode D1 prevents current from flowing back to the logic supply voltage node from the capacitor CB when MOSFET M1 is turned on. In this manner, the boost supply voltage VB is generated and is used to supply some of the high-voltage control circuitry.
The gate driver integrated circuit 11, with or without the power switches M1 and M2 co-packaged therewith, needs protection from electrostatic discharge (ESD) events. ESD events most often occur at the input/output pads or the power supply pins of an integrated circuit. ESD spikes can reach up to several thousand volts and can destroy circuitry within an integrated circuit. Accordingly, integrated circuits frequently include some kind of protection circuit for preventing high voltage ESD spikes to input/output/supply pads from reaching internal circuitry and causing permanent damages.
In particular, for high voltage gate driver circuit 10, ESD protection circuits are needed for input/output pads and supply voltage pads associated with the high-side gate driver circuit. Typically, ESD protection circuits are provided to the boost node BST, the floating supply voltage node LX, and the high input supply voltage VIN node 40. When the power switches are not co-packaged, the high-side drive signal HO output node 25 also needs ESD protection. But even when the power switch is co-packaged, coupling capacitance between the source and the gate of the power switch M1 may allow the ESD current to reach the high-side drive signal output node 25, damaging the transistors of the gate driver 24. Therefore ESD protection is often provided to the HO node 25 as well.
Conventional ESD protection circuits rely on one or more p-n junction diodes to trigger an associated bipolar transistor connected to the input/output pad to shunt the ESD spikes to either a supply voltage node or to the ground node. For example, conventional ESD protection circuits include Zener-triggered NPN bipolar transistor, or grounded-gate NMOS transistor, or RC-gated NMOS transistor. Conventional ESD protection circuits are passive circuits and rely on breakdown of the protection transistor to shunt the current. FIG. 2 illustrates the ESD protection circuits incorporated into high-side control circuitry of the high voltage gate driver circuit of FIG. 1. In FIG. 2, only the high-side control circuitry of high voltage gate driver circuit 10 is shown and other circuit elements in driver circuit 10 are omitted to simplify the discussion. Referring to FIG. 2, an ESD protection circuit 50 is provided between the boost node BST and the floating voltage node LX to protect the boost node relative to the floating tub. In the present illustration, an ESD protection circuit 58 is provided from the VIN voltage node (40) to ground and an ESD protection circuit 55 is provided from the floating supply voltage node LX to ground. In the present illustration, the ESD protection circuits 50, 55, 58 are implemented as Zener-triggered NPN bipolar transistors. In other examples, the ESD protection circuit can be implemented as grounded-gate NMOS transistor 60. The gate of the NMOS transistor 60 can be grounded with or without a resistor.
ESD events often occur during manufacturing, testing or handling when the driver integrated circuit is not powered up. In that case, the NMOS transistor M4 of the gate driver circuit 24 or the NMOS transistor M3 of the pre-driver circuit 22 are most susceptible to failure as NMOS transistors break down and snap back as a result of the high current excursion while the transistors are not turned on. PMOS transistors M5 and M6 do not suffer from failures as PMOS transistors do not snap back. As such, an ESD event at the driver integrated circuit often results in failures at the NMOS transistor M3 or M4. Accordingly, integrated circuit design rules dictate ESD compliant layout for NMOS transistors M3 and M4 where drain and source ballasting is used to ease the high current and high power dissipation resulting from an ESD event while the NMOS transistors are turned off. Drain ballasting increases the size of the NMOS transistor device as a larger distance is imposed from the drain contact to poly gate. Because of ESD compliant layout, the NMOS transistors for the pre-driver and gate driver circuit for a high-side power switch are typically large in size and consume a large amount of silicon real estate.